RISC-V @risc_v Twitter profile

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RISC-V

@risc_v

6 years

. @OpenSingularity ’s Skynet Project, a network of intelligent machines using blockchain, #IoT & #AI , is making a core chip based on @risc_v . @ndahad shares more on @eetimes :

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RISC-V

@risc_v

6 years

Next week’s @risc_v Bay Area Meetup will feature @Google discussing @TensorFlow Lite on @risc_v , @antmicro discussing Renode and @hex_five discussing embedded security! Join us on Nov. 1 in Milpitas, Calif. at @westerndigital :

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RISC-V

@risc_v

4 months

Happy Valentine's Day! ❤️ Spread the love for #RISCV by sharing this post or image!

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RISC-V

@risc_v

4 years

. @oe1cxw of @symbiotic_eda is the winner of this year’s RISC-V Board of Directors Technical Leadership Award. @risc_v is honored to recognize her achievements in the emerging open source EDA tools ecosystem.

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RISC-V

@risc_v

1 year

Milk-V Technology is preparing to launch a high-performance #RISCV computer. The 64-core Milk-V Pioneer supports up to 128GB of RAM in user-upgradable DDR4 DIMM modules. @Hacksterio has more: #RISCVeverywhere #InTheNews

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RISC-V

@risc_v

3 years

This is very exciting! 🎉 Congratulations @beagleboardorg @seeedstudio ! And it runs #linux ! 🥳

BeagleBoard.org

@beagleboardorg

3 years

Along with @SeeedStudio and StarFive, @BeagleBoardOrg just announced BeagleV™—an affordable 64-bit multicore @RISC_V credit-card sized computer designed to run @LinuxFoundation #Linux . Discover more at .

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RISC-V

@risc_v

3 years

6,000 RISC-V Cores on a Xilinx FPGA Break the CoreScore World Record!

6,000 RISC-V Cores on a Xilinx FPGA Break the CoreScore World Record

The 6,000 SERV cores demonstrate Xilinx's FPGA flexibility

www.tomshardware.com

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RISC-V

@risc_v

2 years

Big news, it’s the industry’s first native #RISCV development laptop! Today DeepComputing and Xcalibyte opened preorders for the ROMA development platform. Learn more: #RISCVeverywhere

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RISC-V

@risc_v

7 months

. @Enclustra ’s @MicrochipTech PolarFire SoC FPGA-based module cuts development time from years to months. Read the latest #RISCV #blog to learn more about the Mercury+ MP1 SoM: #RISCVeverywhere

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RISC-V

@risc_v

1 year

At this week’s #RISCVSummitEurope , @risc_v member SOPHGO donated 50 Pioneer Boxes to be shared with the #RISCV ecosystem. #SOPHGO is committed to furthering the advancement of the open standard ISA and its supporting software ecosystem. Learn more:

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RISC-V

@risc_v

1 year

. @Canonical published the optimized Ubuntu release for StarFive’s VisionFive 2, a high-performance #RISCV single board computer with an integrated GPU. Learn more: #RISCVeverywhere

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RISC-V

@risc_v

5 years

. @Google announced its commitment to foster an open source silicon community for hardware and chip design. Read more on @9to5Google :

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RISC-V

@risc_v

7 months

. @beagleboardorg launched the BeagleV®-Fire, a new SBC that opens up new horizons for developers, tinkerers and more to explore the vast potential of #RISCV architecture and FPGA technology: #RISCVeverywhere

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RISC-V

@risc_v

5 years

Check out @aallan ’s article on @Raspberry_Pi joining the @risc_v Foundation @Hacksterio :

Raspberry Pi Becomes a Member of the RISC-V Foundation

Earlier today we had a bit of a surprise with the news that Raspberry Pi has joined the RISC-V Foundation as a member.

www.hackster.io

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RISC-V

@risc_v

11 months

. @beagleboardorg released BeagleV® Ahead, a new single board computer based on TH1520, a quad core 64-bit #RISCV SoC from T-Head. Learn more about this innovative board designed for AI applications, the IoT, and much more.

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RISC-V

@risc_v

2 years

Intel has been a leader in microprocessor innovation for decades and today’s announcements signal that massive investment in #opensource has the power to change the course of history. Welcome Intel as #RISCV newest Premier member!

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RISC-V

@risc_v

7 years

RT @HacksterPro : The new @SiFiveInc Arduino Cinque packs a @RISC_V core along with ESP32 chip for WiFi + Bluetooth

SiFive Unveils the First RISC-V-Based Arduino

In their quest to democratize access to custom silicon, SiFive has announced the very first RISC-V-based Arduino just hours before the…

www.hackster.io

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RISC-V

@risc_v

4 years

Today is @risc_v ’s 10th birthday! Stay tuned for more content that illustrates the evolution of our organization:

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RISC-V

@risc_v

4 years

Looking for a @risc_v for beginners guide tutorial? @BahadirBalban provides a 15 minute introduction with assembly language for beginners here:

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RISC-V

@risc_v

5 years

Today we announced the ratification of the @risc_v base ISA and privileged architecture specifications, marking a milestone for the growing RISC-V ecosystem. Learn more:

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RISC-V

@risc_v

8 months

📢 @Synopsys Launches new RISC-V ISA-based ARC-V™ Processor IP Learn how Synopsys has combined proven processor IP and tools experience with a rapidly expanding ecosystem to accelerate your #RISCV based SoC designs #RISCVeverywhere

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RISC-V

@risc_v

2 months

Renesas will be giving away 100 development boards based on their new R9A02G021 MCU at their talk in the RISC-V Demo Theatre, 4pm, Hall 5, Stand 5-119! #RISCVEverywhere #ew2024

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RISC-V

@risc_v

1 year

Thank you to the global #RISCV community for an incredible year! We look forward to seeing what new heights we can all achieve as we work to bring #RISCVeverywhere .

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RISC-V

@risc_v

1 year

Happy New Year from RISC-V International! Wishing you all a wonderful year ahead. #2023

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RISC-V

@risc_v

4 months

According to The SHD Group, RISC-V is projected to be in billions of devices, gaining significant market penetration. @EETimes_EU has more on #RISCV ’s growth in Europe and across industries: #RISCVeverywhere

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RISC-V

@risc_v

3 years

The second edition of David Patterson and John L Hennessy’s book, “Computer Organization and Design RISC-V Edition: The Hardware Software Interface,” is now available. Get your copy today to learn more about @risc_v uses in modern computing environments:

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RISC-V

@risc_v

6 years

The new QEMU 2.12.0 is the first official QEMU version to contain a @risc_v port and also supports @Raspberry_Pi 3. Learn more:

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RISC-V

@risc_v

1 year

📍Barcelona, Spain #RISCVSUMMITEUROPE starts tomorrow! Will you be joining us? #RISCV #RISCVEverywhere

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RISC-V

@risc_v

5 years

Europe’s first homegrown #HPC processor incorporates @risc_v in a multi-tile package to power Europe’s first exascale #supercomputers . Read more about the @EuProcessor Initiative’s latest project: . #AI

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RISC-V

@risc_v

4 years

A team from @tokyotech_en has developed a portable and Linux-capable @RISC_V system-on-chip (SoC) design that has been designed for both education and potential use in #accelerators . Learn more here:

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RISC-V

@risc_v

3 months

The demand for RISC-V expertise is soaring - stand out in the crowd. Get certified, showcase your skills and advance your career! Find out more here: 💼 🌎 #LearnRISCV #RVFAcertification #RISCVeverywhere

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RISC-V

@risc_v

8 months

. @Android has added RISC-V to its list of CPU architectures that it supports. You can now build, test, and run the Android support for RISC-V on your own machine! Learn more about @Google 's announcement here: and at #RISCVSummit !

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RISC-V

@risc_v

3 years

Learn about how to build a #RISCV CPU from scratch. @ten_filip of @IEEESpectrum walks you through how to do this here:

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RISC-V

@risc_v

1 year

. @Mips_Tech and @siemenssoftware are collaborating to speed time-to-market and accelerate software development for customers of the new MIPS eVocore P8700 #RISCV multiprocessor. Learn more: #RISCVeverywhere

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RISC-V

@risc_v

8 months

There’s a ton of activity going on in the #RISCV developer community! To see some of the action, check out the RISC-V Developer Zone at the #RISCVSummit . Submit your #RISCV dev board to be showcased in the Zone here: #RISCVeverywhere

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RISC-V

@risc_v

3 years

Today @Canonical announced their first @Ubuntu release for two of @SiFive ’s most prominent boards: Unmatched and Unleashed. Read more about it here:

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RISC-V

@risc_v

6 months

Introducing Quintauris! Industry leaders @BoschGlobal , @Infineon , @NordicTweets , @NXP , and @Qualcomm announced the establishment of Quintauris, a company aimed to advance the adoption of #RISCV by enabling next-gen hardware development. Read on:

Five Leading Semiconductor Industry Players Incorporate New Company, Quintauris, to Drive RISC-V...

Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor ASA, NXP® Semiconductors, and Qualcomm Technologies,

www.businesswire.com

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RISC-V

@risc_v

5 years

. @SiFive added @ImaginationTech ’s PowerVR GPU and neural network accelerator IP cores to its design platform. Read more:

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RISC-V

@risc_v

8 months

“We're already in billions of cores around the world and some analysts have even pointed out that it's actually getting hard to find any new design starts that don't include RISC-V … RISC-V is the most profound technical revolution of our time.” – @Calista_Redmond #RISCVSummit

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RISC-V

@risc_v

5 months

“The age of full-fledged RISC-V data center CPUs is nearly upon us...” @VentanaMicro ’s #RISCV CPU, Veryon V2, offers higher performance than what is possible with a traditional CPU without hardware acceleration. @tomshardware has more: #RISCVeverywhere

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RISC-V

@risc_v

4 years

Norwegian healthcare-focused #IoT specialist ONiO has unveiled , an ultra-low-power @risc_v based microcontroller capable of operating wholly from harvested energy:

ONiO.zero Offers Up to 24MHz of RISC-V Microcontroller Performance on Nothing But Harvested Energy

No batteries, no supercapacitors, no problem: ONiO claims its design can harvest power from the radio spectrum to operate at up to 24MHz.

www.hackster.io

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RISC-V

@risc_v

6 years

Check out this implementation of the @risc_v ISA, which showcases the powerful modeling techniques provided by Transaction-Level Verilog. Read more about WARP-V on @Hacksterio :

WARP-V: The Most Flexible RISC-V CPU Core Generator

WARP-V is an implementation of the RISC-V ISA that showcases the powerful modeling techniques provided by Transaction-Level Verilog.

www.hackster.io

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RISC-V

@risc_v

4 years

. @BSC_CNS has coordinated the manufacture of the first open source chip developed in Spain, the @risc_v based Lagarto chip, built with TSMC’s 65-nanometer transistors:

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RISC-V

@risc_v

5 months

Announcing the enhanced version of our "Introduction to RISC-V" course! We've carefully listened to your feedback and made significant improvements to deliver an even more enriching learning experience. Dive into the upgraded content: #LearnRISCV

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RISC-V

@risc_v

4 years

Celerity, a multi-university effort, has resulted in an open-source manycore #RISCV tiered accelerator chip. Read up on their second-gen 496-Core @RISC_V Mesh NoC here:

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RISC-V

@risc_v

6 years

With the news regarding #meltdown and #spectre , here's a view from the @risc_v Foundation

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RISC-V

@risc_v

3 years

The Future of #RISCV Has No Limits! #RISCVSummit

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RISC-V

@risc_v

5 years

The @EuProcessor Initiative plans to develop a low-power microprocessor using @risc_v architecture for exascale supercomputers, data centers and the automotive market. Read more:

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RISC-V

@risc_v

4 years

Computers powered by @risc_v ! @VentureBeat ’s @deantak wrote about @SiFive ’s HiFive Unmatched, a platform for Linux-based personal computers based on #RISCV processors. Read the article here:

SiFive unveils plan for Linux PCs with RISC-V processors

SiFive today announced it is creating a platform for Linux-based personal computers based on RISC-V processors.

venturebeat.com

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RISC-V

@risc_v

10 months

. @openhwgroup announced that the OpenHW CORE-V MCU DevKit, a comprehensive Development Kit for an open-source #RISCV MCU, is now available to be ordered. The DevKit enables software development for embedded, IoT, and AI-driven applications. Learn more:

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RISC-V

@risc_v

1 year

. @SipeedIO posted images teasing a new single-board computer based on a #RISCV processor boasting the ratified RISC-V Vector Extension 1.0. Read more: via @Hacksterio #RISCVeverywhere

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RISC-V

@risc_v

6 years

We’re excited to share that the @risc_v Foundation and the @linuxfoundation have announced a joint collaboration to enable a new era of open architecture and accelerate adoption of the @risc_v ISA. Read more:

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RISC-V

@risc_v

7 months

Want to see a #RISCV based smartwatch, tablet, or laptop? What about RISC-V dev boards? Make sure to stop by the #RISCVSummit Developer Zone. If you’re not at the show, check out to see some of the latest RISC-V offerings. #RISCVEverywhere

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RISC-V

@risc_v

7 months

Read @EETimes_EU ’s article to learn why #RISCV is an exciting development for hardware-assisted verification vendors and how the RISC-V ecosystem can build a rich verification environment that designers can trust: #RISCVeverywhere

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RISC-V

@risc_v

3 months

. @Tenstorrent and Japan’s Leading-edge Semiconductor Technology Center (LSTC) have partnered to co-design a chip that will redefine #AI performance in Japan. Learn more about the announcement here:

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RISC-V

@risc_v

4 years

Wow, we are inspired by this 13-year-old! A new blog by @RedwoodEDA ’s @SteveHoover99 tells the story of Nicholas Sharkey who successfully completed his 5-stage pipelined @risc_v CPU core. Read more here:

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RISC-V

@risc_v

6 years

Congrats to the winners of the @risc_v SoftCPU contest: Charles Papon with VexRiscv in 1st place, Antti Lukats with Engine-V in 2nd place, Changyi Gu with PulseRain Reindeer in 3rd place and Olof Kindgren with SERV for the Creativity prize. Thanks to all who participated! #riscv

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RISC-V

@risc_v

1 year

Want to see some of the latest and greatest #RISCV dev boards? Head on over to @electronicdesgn to see their roundup: #RISCVeverywhere

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RISC-V

@risc_v

2 months

. @sundancedsp_inc ’s SoM1-SOC is a feature-rich RISC-V-based SOCs available in the market. The SoM offers a high level of security, performance and efficiency for embedded systems development. Learn more: #RISCVeverywhere

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RISC-V

@risc_v

5 years

. @XFAB_FOUNDRY and @efabless have announced the first silicon availability Raven, an open source SoC reference design based on the PicoRV32 @risc_v core. Learn more about the open source design:

X-FAB, Efabless Release First Silicon of Raven RISC-V SoC - Embedded Computing Design

A mixed-signal SoC, nearly 75 percent of Raven?s die area leverages X-FAB analog IP and standard macros. Simulations project a maximum clock speed of 150 MHz.

embeddedcomputing.com

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RISC-V

@risc_v

2 years

Intel Pathfinder for RISC-V just launched to “transform the way SOC architects and system software developers define new products.” Read more about this big announcement and check out all the ecosystem partners who are involved below.

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RISC-V

@risc_v

4 years

New blog! @abhi99jadhav walks through RIOS laboratory’s #RISCV small-board computer, PicoRio, hinting at what we can expect in the upcoming versions and more. Learn more about this very affordable and powerful board to develop #CPU cores. Read here:

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RISC-V

@risc_v

6 years

This project can program a PicoRV32 @risc_v softcore with Ada, a softcore that runs on a @latticesemi ICE40LP8K-based TinyFPGA-BX #FPGA Board. Learn more on @hackaday :

Programming A RISC-V Softcore With Ada

We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based …

hackaday.com

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RISC-V

@risc_v

4 years

. @EspressifSystem announced that its next-generation ESP32-S2 #SoC , modules and related development boards that come with an ultra-low-power @risc_v coprocessor built into the RTC block are now in mass production. Learn more here:

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RISC-V

@risc_v

2 months

Excited to share another remarkable day at embedded world 2024! Day 2 showcased enlightening discussions facilitated by members of @risc_v , along with an array of giveaways and freebies (RISC-V socks? Yes, please! 🧦), and a bustling board zone filled with activity 🚀 #ew24

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RISC-V

@risc_v

2 years

. @StarFiveTech completed production and testing of the first batch of #RISCV VisionFive 2 SBCs and is starting shipments. Find out more: #RISCVSummit

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RISC-V

@risc_v

3 years

Thank you to the #RISCV team for doing amazing things from providing guidance at the information booth to sharing insights in their keynotes at the #RISCVSummit . @Calista_Redmond , @stephano , @kamcmahon , @TheaClay , @mark_riscv , Brett Preston, Jeff Scheel, and Megan Lehn.

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RISC-V

@risc_v

9 months

From a native RISC-V powered laptop to a robot powered by a RISC-V chipset, @DeepComputing has introduced innovative #RISCV products and achieved significant advancements in the realm of high computing power with RISC-V technology. Learn more here:

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RISC-V

@risc_v

11 months

#ICYMI The Debian Project announced that the RISC-V (riscv64) hardware architecture is now officially supported by the Debian GNU/Linux operating system! @9to5linux has more on the announcement here: #InTheNews #RISCVeverywhere

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RISC-V

@risc_v

1 year

“Are we open source or open standard? We are open standard.” - @mark_riscv #RISCV #RISCVSUMMITEUROPE #RISCVEverywhere

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RISC-V

@risc_v

5 years

Researchers at @MIT used carbon nanotubes to make a general purpose, @risc_v compliant processor that handles 32-bit instructions and 16-bit memory addressing. @Electronicsnews shares an update on the recent news.

More on: MIT's carbon nanotube RISC-V CPU

Last week MIT announced a CPU made from carbon nano-tube (CNT) mosfets using standard CMOS fab equipment and only the materials and processes found within

www.electronicsweekly.com

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RISC-V

@risc_v

5 years

We’re launching the RISC-V Soft CPU Contest, sponsored by @MicrochipTech and @thalesgroup , to advance the development of more robust security solutions. Get the details and learn how you can enter:

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RISC-V

@risc_v

5 months

Responding to community feedback, we're excited to relaunch the improved version of the "Introduction to RISC-V" course, incorporating your valuable input. Elevate your learning: #LearnRISCV #RISCVcommunity #FREEonlineCourse

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RISC-V

@risc_v

5 years

Check out @westerndigital ’s new prototype board, Houdini, unveiled during Martin Fink’s keynote. To learn more, be sure to stop by the @westerndigital booth.

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RISC-V

@risc_v

1 year

“RISC-V chips have already begun to pop up in earbuds, hard drives, and AI processors, with 10 billion cores already shipped.” @sophurky discussed why #RISCV is one of @techreview 's 10 Breakthrough Technologies of the year: #RISCVeverywhere

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RISC-V

@risc_v

3 years

“The rise of RISC-V cannot be ignored.” @WilliamLi_CY of @CounterPointTr ’s shares his insights from a recent report, stating how #RISCV will shake up the $8.6-Billion #semiconductor IP market. Read more here:

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RISC-V

@risc_v

3 years

#RISCV ambassador, @pdp7 , sports his #RISCVFashion while listening to a demo at our booth!

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RISC-V

@risc_v

1 month

🥳It's time to celebrate RISC-V's birthday! Can you believe it? RISC-V is turning 14 this Saturday! We've got a packed week of exciting activities. Anything catching your eye? #RISCV #RISCVeverywhere

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RISC-V

@risc_v

4 years

Download your 64-bit super-scalar RISC-V processor in full source code from @cobhamgaisler today! Check it out here:

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RISC-V

@risc_v

1 year

Software engineer and Cornell PhD candidate Yunhao Zhang has developed an operating system that packs an entire #RISCV operating system into just 2,000 lines of code. @Hacksterio has more details: #RISCVeverywhere #InTheNews

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RISC-V

@risc_v

3 years

Wishing you the best during this holiday season. See you all in 2021!

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RISC-V

@risc_v

5 months

“If RISC-V succeeds, the world is a better place.” - Dale Greenley of Ventana Micro Systems Listen to leaders from @arteris_noc , @synopsys , @tenstorrent , and @VentanaMicro discuss chiplets in the RISC-V ecosystem and how #RISCV enables new technologies:

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RISC-V

@risc_v

6 years

. @SiFiveInc ’s new @risc_v based HiFive Unleashed SBC runs Linux and is now available for pre-sales. @LinuxGizmos shares more:

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RISC-V

@risc_v

2 years

David Patterson, vice chair of the @risc_v Board of Directors, wrote about the five myths around #RISCV and how by the end of this decade, the dominant ISA for future product development will be the open RISC-V architecture. Check it out at @eetimes :

Examining the Top Five Fallacies About RISC-V - EE Times

Companies are already designing with RISC-V and the momentum is rapidly increasing, so this is a good time for the industry to take a closer look.

www.eetimes.com

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RISC-V

@risc_v

4 years

India has announced a national competition to drive the growth of RISC-V microprocessor designs with local students and startups. Learn more about the competition via @TheRegister :

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RISC-V

@risc_v

5 years

We’re excited to welcome @RedHat to the @risc_v Foundation. Learn more at @phoronix :

Red Hat Joins The RISC-V Foundation

Red Hat has joined the RISC-V Foundation to help foster this open-source processor ISA.

www.phoronix.com

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RISC-V

@risc_v

1 year

Taking place from June 5-9 in Barcelona, #RISCVSummitEurope will be the premier event that connects the movers and shakers that are building the future of innovation on #RISCV . Register here: #RISCVeverywhere

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RISC-V

@risc_v

5 years

. @debian contributor and developer Manuel A. Fernandez Montecelo announced an update on the status of the @debian GNU/Linux @risc_v 64 port. Learn more about the significance of this project:

Debian GNU/Linux port for RISC-V 64-bits: Why it matters and roadmap | Packt Hub

Manuel A. Fernandez Montecelo, a Debian contributor and developer talked about the Debian GNU/Linux riscv64 port at the RISC-V workshop.

hub.packtpub.com

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RISC-V

@risc_v

4 years

“We are enthusiastic users of both ARM and @risc_v . They are very different things.” – Jensen Huang, CEO of @nvidia . Read @peterclarke88 of @eeNewsEurope ’s coverage on the recent news here:

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RISC-V

@risc_v

2 years

Congratulations to the @risc_v award winners! We appreciate all of your contributions to the #RISCV community. Here’s a snapshot of some of our winners; stay tuned for more details. #RISCVSummit

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RISC-V

@risc_v

3 years

What does it look like to program with no operating system? Learn how modern C++ is a great way to explore #RISCV and develop embedded systems here:

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RISC-V

@risc_v

1 year

#ICYMI @Canonical announced that Ubuntu is available on a high-performance #RISCV SBC with an integrated GPU. Learn more about the StarFive VisionFive 2: #RISCVeverywhere

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RISC-V

@risc_v

3 months

In today's rapidly evolving tech landscape, maintaining trust and security is paramount. Check out this insightful read from the team at @ImaginationTech about the role SoC security plays in safeguarding digital integrity ➡️

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8

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RISC-V

@risc_v

2 months

Good Morning, Nuremberg! We are on-site at the RISC-V booth at #ew2024 (Hall 5, Stand 5-119). Stop by to chat & enter for a chance to win some fun giveaways!

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RISC-V

@risc_v

5 years

. @cnxsoft shares how users can run Linux on @risc_v on a QEMU emulator using a Berkeley Boot Loader, Linux 4.14 and busybear rootfs.

Getting Started with Embedded Linux on RISC-V in QEMU - CNX Software

Bootlin has published a presentation showing how to build & run embedded Linux RISC-V in QEMU with Buildroot including BBL, Linux, and Busybox

www.cnx-software.com

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RISC-V

@risc_v

3 years

Welcome to the #open era of computing! Stop by the #RISCV booth at #ossummit #lfelc for a special edition t-shirt and say hello to the team!

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7

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RISC-V

@risc_v

1 year

. @antmicro adapted the #OpenTitan configuration to fit into a small, accessible @XilinxInc #Artix7 A200T #FPGA , opening the path to synthesizing this #SystemVerilog design with the #opensource #Yosys /UHDM flow. Read more: @google @chipsalliance

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RISC-V

@risc_v

5 years

Michael Welling of @QwertyEmbedded Design discusses a new update to the @risc_v LoFive R1 breakout. Read more on @Hacksterio :

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15

38

RISC-V

@risc_v

10 months

🎉That's a wrap on Day 1 of #RISCVSummitChina ! From inspiring discussions to engaging sessions, we had a packed day filled with important conversations. We can't wait to see what the rest of the event has in store. #RISCVeverywhere

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RISC-V

@risc_v

5 years

Arjun Menon of @iitmadras talked about the exciting work of the Shakti Project, an open-source processor development initiative by the RISE group at @iitmadras . Read more about the Shakti Project here: #RISCVSummit

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